The present invention relates generally to integrated circuit designs and more particularly to write control circuit design for improving read and write margins in multi-port static random access memory (SRAM).
SRAM is typically used for storing data needed to be speed accessed by processing units. A conventional 6-T SRAM cell comprises two cross-coupled inverters forming a data latch and two pass-gate NMOS transistors for controlling accesses to the data latch by a bit-line-true (BLT) and a bit-line-complementary (BLC). During a read operation, the data latch drives the BLT or BLC to develop a differential voltage between the BLT and BLC, therefore a higher supply voltage provides a greater read margin. During a write operation, it is the BLT or BLC to force the data latch to flip, therefore, given a fixed BLT and BLC voltage level, a lower supply voltage provides a greater write margin.
FIG. 1 illustrates a prior-art SRAM column 100 with the conventional 6-T SRAM cells 102[0:n−1] and two positive voltage power supplies, CVDDHI and CVDDLO, where CVDDHI voltage is higher than CVDDLO voltage. When the SRAM column 100 is in a read operation, a signal YSWHI is asserted a logic LOW voltage while a signal YSWLO remains at a logic HIGH voltage, then the CVDDHI is coupled to a CVDD node to supply power to the SRAM cells 102[0:n−1]. During a write operation, a signal YSWLO is asserted the logic LOW voltage while the signal YSWHI remains at the logic HIGH voltage, the CVDDLO is coupled to the CVDD node.
The aforementioned prior-art system works well in a single port SRAM, where read and write operations occur always in different clock cycles. But in a multi-port SRAM, read and write operations may happen to SRAM cells in the same clock cycle. In this case, increasing read margin requires higher power supply voltage, while increasing write margin requires lower power supply voltage, they contradict with each other and render the prior-art system being unable to increase both read and write margins at the same time.
As such, what is desired is a power supply (VDD) management system that increases both read and write margins at the same time for SRAMs and particularly for dual-port SRAMs.